Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits
نویسندگان
چکیده
Excessive voltage drops in power and ground (P&G) buses of CMOS VLSI circuits can severely degrade both design reliability and performance. Maximum current estimates are needed in the circuit to accurately determine the impact of these problems. In [1], a pattern-independent, linear time algorithm (iMax) is described that is very e ective in estimating the maximum current waveforms at various contact points in the circuit. In [1], the algorithm was demonstrated for simple gate delay and current models. In this paper, we rst derive expressions for modeling delays and current waveforms for a general gate and then describe how the algorithm can be extended under more general models.
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